This application is based upon and claims the benefits of priority from the prior Japanese Patent Application No. 2000-361455, filed on Nov. 28, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing the same. More particularly, it relates to an MIS type semiconductor device having an elevated source/drain structure and a method of manufacturing the same.
2. Description of the Related Art
Currently, integrated circuits formed by integrally arranging a number of transistors and resistors on a semiconductor substrate are popularly being used in essential parts of computers and communication devices. Due to the trend toward a higher degree of integration of devices, many of the dimensions defined by applicable design rules are becoming smaller and smaller. In the case of MIS type semiconductor devices, the diffusion layer is required to be made shallow in order to suppress the short channel effect that arises as a result of a reduced gate length. However, at the same time, the increase in the resistance of the diffusion layer due to the reduced depth thereof has to be avoided. In an attempt at reducing the depth of the diffusion layer and, at the same time, avoiding the resultant increase of the resistance thereof, there has been proposed a technique of combining a structure where only the silicon in the source/drain region is raised, or a so-called elevated source/drain structure, and the use of silicide, which is a compound of silicon and metal, formed in a self-aligning manner (T. Yoshitomi, et al., 1995 Symposium on VLSI Technology Digest of Technical Papers, p. 11).
Several methods have been proposed for forming such an elevated source/drain structure. They include vapor phase epitaxial growth and solid phase epitaxial growth. However, when an epitaxial growth technique is used, facets are produced near the gate oxide film and the element isolation zone to make it impossible to provide a sufficiently large thickness in the vicinity of those areas for the film formed by epitaxial growth. Particularly, as a result of a small thickness of the epitaxially grown film in an area near the gate, impurities can be implanted deep into the substrate in the subsequent ion implantation step to give rise to the problem of a short channel effect. Additionally, the problem of a junction leak arises in the succeeding silicide step because of the short distance from the pn junction. Then, an additional step for forming a side wall on the elevated source/drain region is required to be conducted before the silicide step in order to suppress the leak due to the silicide to consequently increase the number of manufacturing steps. Furthermore, as elements are miniaturized, both the distance between the gate electrode and the source region and the distance between the gate electrode and the drain region are reduced to give rise to a risk of short-circuiting.
Because of the above-identified problems and other problems, there is a strong demand for a semiconductor device having an elevated source/drain structure that has a shallow and low-resistance diffusion layer and is free from the problems of leak and short-circuiting.
An first aspect of the present invention, there is provided a semiconductor device comprising:
a silicon substrate;
a gate insulating film formed on a surface of the silicon substrate;
a gate electrode formed on the gate insulating film;
a first side wall film formed on a side surface of the gate electrode, and extending to the surface of the silicon substrate;
an elevated region formed by epitaxial growth of silicon on the surface of the silicon substrate;
a second side wall film formed on the first side wall film, being made of different material from the first side wall film and separated from the surface of the silicon substrate by the elevated region; and
a source region and a drain region formed in the silicon substrate and having a same conductive type with the elevated region.
A multilayer type side wall films are formed on the respective side surfaces of the gate electrode of each MIS type element such as a transistor or a resistance by laying a number of layers that are directed toward a surface of the silicon substrate. With this arrangement, the leak current that can be generated by the tunnel phenomenon between the gate and the source or the drain is effectively suppressed.
Of the walls, the wall located close to the gate electrode is referred to as the first side wall film and the one formed remote from the gate electrode is referred to as the second side wall film. Then, a gap is formed between the second side wall film and the top surface of the silicon substrate and the materials used for the first side wall film and their equivalents are eliminated from the gap to arrange an elevated source/drain region there in order to reduce the distance between the region and the channel. As a result, the distance between the diffusion layer of the substrate located below the region and the part of the channel located below the gate edge is reduced to by turn reduce both the reach of impurity diffusion and the depth of the diffusion layer in the diffusion layer forming process and consequently suppress the short channel effect.
Both the short channel effect and the leak can be further reduced by suppressing the generation of facets in the epitaxial growth process and by filling the elevated region in the gap between the second side wall film and the silicon substrate. Generally, crystal facets having a specific facet index are formed in the epitaxial growth process to suppress the epitaxial growth in the direction of the facet. Particularly, in the case of solid phase epitaxial growth, the (110) plane grows at a rate about twice as slow as the (100) plane, whereas the (111) plane shows a growth rate twenty times as low as the (100) plane. While a silicon substrate having a (100) plane is generally used, not only a (100) plane but also a (110) plane and a (111) plane that show a low growth rate are formed in the solid phase epitaxial growth process. Similarly, in the case of vapor phase epitaxial growth, a (311) plane is apt to be formed. When the DHF process is insufficient, the epitaxially grown film produces facets due to the gate insulating film. It is believed that the amorphous silicon (to be referred to as a-Si hereinafter) deposited on the insulting film is bonded, if weakly, to atoms of the insulating film and such facets reflect the difference in the bond energy. As a result of a series of experiments conducted by the inventor of the present invention, it is found that such facets are apt to be produced more in the vicinity of a silicon oxide film than in the vicinity of a silicon nitride film. Therefore, if the gate insulating film is formed from an oxide film, facets are formed due to the oxide film but, on the other hand if an epitaxially grown facet is made to contact the lower end of the side wall film of silicon nitride film, it is possible to realize epitaxial growth on the side wall film without forming facets because of the existence of the silicon nitride film. In the case of solid phase epitaxial growth, while the etched region under the second side wall film is completely filled with amorphous silicon and hence facets are formed in the subsequent solid phase epitaxial growth process, all the amorphous silicon filling the etched region is crystallized if the solid phase epitaxial growth process is conducted thoroughly because the epitaxial growth, if slow, takes place also on the facets.
The elevated region can be made to grow in contact with the surface of the second side wall film and also extend under the second side wall film to provide a sufficient film thickness for the epitaxially grown film near the second side wall film so that the silicide film can be sufficiently isolated from the pn junction to satisfactorily suppress any leak attributable to the silicide film.
The structure forming a space surrounded between the first side wall film and the elevated region isolates the elevated source/drain from the gate electrode by the space with a low dielectric constant to reduce the parasitic capacitance.
In another aspect of the invention, a multilayer film structure, or a structure having a plurality of side wall films, is formed in at least part of the area between the gate electrode and the elevated source/drain region by means of a method as described below.
Namely, in the aspect of the invention, there is provided a method of manufacturing a semiconductor device comprising:
forming a gate insulating film on a silicon substrate;
forming a gate electrode on the gate insulating film;
forming a first insulating film to cover the gate insulating film and the gate electrode;
forming a second insulating film on the first insulating film with a material different from that of the first insulating film;
selectively leaving the second insulating film on a side surface of the gate electrode with the first insulating film interposed therebetween by etching a surface of the second insulating film and using the first insulating film as etching stopper;
exposing the surface of the silicon substrate by removing the first insulating film not covered with the second insulating film;
forming an elevated region on the exposed surface of the silicon substrate by epitaxial growth of silicon; and
changing at least a surface layer of the elevated region into metal silicide film.
The above method may be partly modified so as to make the epitaxially grown film contain a conductive type impurity by causing gas containing the conductive type impurity substance to flow in the epitaxial growth step. Then, the operation of ion implantation and that of partly removing the side wall films can be omitted to simplify the overall process.